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SUMMIT
MICROELECTRONICS, Inc.
S9518
Nonvolatile DACPOTTM Electronic Potentiometer With Debounced Push Button Interface
FEATURES Digitally Controlled Electronic Potentiometer * 8-Bit Digital-to-Analog Converter (DAC) - Independent Reference Inputs - Differential Non-Linearity - 0.5LSB max - Integral Non-Linearity - 1LSB max * VOUT Value in EEPROM for Power-On Recall - Equivalent to 256-Step Potentiometer * Unity Gain Op Amp Drives up to 1mA * Simple Trimming Adjustment - Debounced Push Button Interface * Low Noise Operation * "Clickless" Transitions between DAC Steps * No Mechanical Wearout Problem - 1,000,000 Stores (typical) - 100 Year Data Retention * Operation from +2.7V to +5.5V Supply * Low Power, 1mW max at +5V
OVERVIEW The S9518 DACPOT trimmer is an 8-bit nonvolatile DAC designed to replace mechanical potentiometers. The S9518 includes a unity-gain amplifier to buffer the DAC output and enables VOUT to swing from rail to rail. The DACPOT trimmer operates over a supply voltage range of 2.7V to 5.5V. The S9518's simple push button input provides an ideal interface for operator adjusted equipment. This interface allows for quick and easy adjustment of even the most sophisticated systems. The S9518 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. The S9518 offers double the resolution of these devices and provides `clickless' transitions of VOUT.
FUNCTIONAL BLOCK DIAGRAM
VDD VH
8-bit E2PROM
Debounce Circuit & Write Control Logic
8-bit Data Register
8-bit DAC
VOUT
VL
UP DWN STR
GND
2017 ILL2.2
SUMMIT MICROELECTRONICS, Inc.
*
300 Orchard City Drive, Suite 131
*
Campbell, CA 95008
*
Telephone 408-378-6461
*
Fax 408-378-6586
*
www.summitmicro.com
(c) SUMMIT MICROELECTRONICS, Inc. 1999 2017-04 4/24/99
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Characteristics subject to change without notice
S9518
PIN NAMES Symbol UP DWN VH GND VOUT VL STR VDD Description PB Input, Moves VOUT Toward VH Input PB Input, Moves VOUT Toward VL Input Vref High Ground Trimmed Voltage Output Vref Low Store Input, Providing a Control Input to Initiate a Store Operation Supply Voltage (2.7V to 5.5V)
2017 PGM T1.0
PINOUT
UP DWN VH GND
1 2 3 4
8 7 6 5
VDD STR VL VOUT
2017 ILL1.1
Analog Section The S9518 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 8-bit digital values into equivalent analog output voltages in proportion to the applied reference voltage. Reference Inputs The voltage differential between the VL and VH inputs sets the full-scale output voltage range. VL must be equal to or greater than ground (a positive voltage). VH must be greater than VL and less than or equal to VDD. See specifications on page 5 for guaranteed operating limits. Output Buffer Amplifier The voltage output is from a precision unity-gain follower that can slew up to 1V/s. Digital Interface The interface provides simple push button control of an up/down counter that drives the DAC. The DAC output is a ratiometric voltage output. UP is an active low push-button input. An internal pull-up resistor, with nominal value of 50kohm, eliminates an external resistor that would be required with push button control. A 30ms debounce period is included in the input timing to prevent multiple pulsing of the counter. Either a switch closure to ground or a LOW logic level will, after the debounce time, change the potentiometer tap position. UP moves the output voltage towards the VH reference input. If the UP push-button is kept depressed, the counter will continue to increment at the rate of one count every 250ms for one second. After one second the
counter increments faster, one count every 50ms, until the push-button is released. Changes to the DAC output using the UP input do not alter the data stored in EEPROM. The STR input updates the nonvolatile EEPROM memory. DWN is an active low push-button input that decrements the counter and moves the potentiometer output voltage towards the VL reference input. The DWN control input also includes an internal 50kohm pull-up resistor and a 30ms debounce period to prevent multiple pulsing. A LOW logic level will also change the potentiometer tap position after the debounce period. If the DWN pushbutton is kept depressed, the counter continues to decrement at the rate of one count every 250ms for one second. After one second the counter decrements at one count every 50ms until the push-button is released. Changes to the DAC output using the DWN input do not alter the data stored in EEPROM. STR This input can be used in two ways: 1) If the input is tied LOW, then AUTOSTORE is enabled. When VDD powers-down an automatic store cycle takes place that updates the nonvolatile EEPROM memory. 2) STR is an active low push-button input that also updates the nonvolatile memory. The input is debounced but does not have an internal pull-up resistor. For every valid push, the S9518 will store the current potentiometer position to EEPROM.
2017-04 4/24/99
2
S9518
DEVICE OPERATION There are five main blocks to the S9518: an 8-bit EEPROM memory; input debounce circuits, control logic, and 8-bit counter; 8-bit data register; decode section and resistor ladder (DAC); and the buffer amplifier. The input control section operates just like an up/down counter. The output of this counter is fed to the data register and then decoded to activate one of 255 electronic switches connected to the resistor ladder. Each switch connects a point on the ladder to the buffer amplifier input. When requested, the contents of the counter can be stored in EEPROM memory and retained for future use. The ladder is comprised of 256 resistors of equal value connected in series. At the bottom of the ladder and at the junctions of the resistors there are electronic switches that transfer the voltage at each point to the buffer amplifier and hence to the output. The S9518 is designed to interface directly to two push button switches that effectively move the potentiometer wiper up or down. The UP and DWN inputs increment or decrement the 8-bit counter respectively. The data input to the DAC is decoded to select one of the 256 wiper positions along the resistive ladder. The wiper increment input, UP and the wiper decrement input, DWN are connected to internal pull-ups so that they normally remain HIGH. When pulled LOW by an external push button switch or a logic LOW level input, the wiper will be switched to the next adjacent tap position. Internal debounce circuitry prevents inadvertent switching of the wiper position if UP or DWN remain LOW for less than 30ms (typical). Each of the buttons can be pushed either once for a single increment/decrement or held low continuously for a multiple increments/decrements. The number of increments/decrements of the wiper position Figure 1: Typical circuit with STR store pin used in AUTOSTORE mode depends on how long the button is pushed. When making a continuous push, after the first second, the increment/ decrement speed increases. For the first second the device will be in the slow scan mode. Then if the button is held for longer than one second the device will go into the fast scan mode. As soon as the button is released the S9518 will return to a standby condition. The DAC, whether set to 00 or FF, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked beyond FF or below 00. AUTOSTORE The value of the counter is stored in EEPROM memory whenever the chip senses a power-down of VDD while STR is enabled (held LOW). When power is restored, the contents of the memory are recalled and the counter reset to the last value stored. If AUTOSTORE is to be implemented, STR is typically hard wired to GND. If STR is held HIGH during power-up and then taken LOW, the wiper will not respond to the UP or DWN inputs until STR is brought HIGH and the store is complete. Figure 1. Manual (Push Button) Store When STR is not enabled (held HIGH) a push button switch may be used to pull STR LOW and released to perform a manual store of the wiper position in EEPROM memory. Figure 2. Effect of VDD Removal The resistor ladder, connected between VH and VL, does not change value when VDD is removed. However, the buffer amplifier no longer functions and consequently a high impedance appears at the VOUT pin. Figure 2: Typical circuit with STR store pin controlled by push button switch
VCC
3.3F
8 1 2 7 4 3 5 6
VCC
8 1 VDD UP DWN STR VH 3 VOUT 5 VL 6 GND
VDD UP DWN STR
GND VH VOUT VL
20K
2 7
2017 ILL4.0
2017 ILL3.0
2017-04 4/24/99
3
S9518
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Storage Temperature Voltage on pins with reference to GND: Analog Inputs Digital Inputs Analog Outputs Digital Outputs Lead Solder Temperature (10 secs) -55C to +125C -65C to +150C -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V 300C *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RECOMMENDED OPERATING CONDITIONS Condition Temperature VDD
Min -40C +2.7V
Max +85C +5.5V
2017 PGM T2.2
2017-04 4/24/99
4
S9518
DAC DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40C to +85C, unless specified otherwise
Symbol Parameter Integral Non-Linearity Differential Non-Linearity VrefH Input Voltage VrefL Input Voltage VrefH to VrefL Resistance Temperature Coefficient of RIN Full-Scale Gain Error VrefH to VrefL DATA = FF 0 -200 10 20 90 0.08 300 1 Conditions ILOAD = 100A, ILOAD = 100A, Guaranteed but not tested Min. VrefL Gnd Typ. 0.5 0.1 38k 600 Max. 1 0.5 VDD VrefH 1 20 50 +1000 Units LSB LSB V V ppm/C LSB mV V/C A LSB/V nV/ % kHz
2017 PGM T3.4
Accuracy
INL DNL
References VH
VL RIN TCRIN
Analog Output
GEFS VOUTZS TCVOUT
Zero-Scale Output Voltage DATA = 00 VOUT Temperature Coefficient Amplifier Output Load Current Amplifier Output Resistance ILOAD = 100A VDD = +5V VDD = +3V Power Supply Rejection Amplifier Output Noise Total Harmonic Distortion Bandwidth - 3dB ILOAD = 10A f = 1kHz, VDD = +5V VIN = 1V rms, f = 1kHz VIN = 100mV rms VDD = +5, ILOAD = 50A, VrefH = +5V, VrefL = 0V Guaranteed but not tested
IL ROUT PSRR eN THD BW
HZ
RELIABILITY CHARACTERISTICS Symbol VZAP ILTH TDR NEND Parameter ESD Susceptibility Latch-Up Data Retention Endurance Min 2000 100 100 1,000,000 Max Unit V mA Years Stores Test Method MS-883, TM 3015 JEDEC Standard 17 MS-883, TM 1008 MS-883, TM 1033
2017 PGM T4.0
2017-04 4/24/99
5
S9518
DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, Unless otherwise specified Symbol IDD ISB IIH IIL VIH VIL
Notes: 1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference resistor chain. 2. UP and DWN have internal pull-up resistors of approximately 50k. When the input is pulled to ground the resulting output current will be VDD/50k.
Parameter Supply Current during store, note 1 Supply Standby Current Input Leakage Current Input Leakage Current, note 2 High Level Input Voltage Low Level Input Voltage
Conditions STR =
Min
Max 1.2 200
Units mA A A A V V
2017 PGM T5.1
VIN = VDD VIN = 0V 2 0
10 -100 VDD 0.8
AC OPERATING CHARACTERISTICS VDD = +4.5V to +5.5V Limits Symbol fGAP tDB tS SLOW tS FAST tPU tR VDD tASTO tASTH tASEND Parameter Time Between Two Separate Push Button Events Debounce Time After Debounce to Wiper Change on a Slow Mode Wiper Change on a Fast Mode Power-Up to Wiper Stable VDD Power-Up Rate AUTOSTORE Cycle Time AUTOSTORE Threshold Voltage AUTOSTORE Cycle End Voltage 0.2 2 4 3.5 100 25 Min. 0 30 250 50 60 375 75 500 50 Typ. Max. Units s ms ms ms s mV/s ms V V
2017 PGM T6.0
2017-04 4/24/99
6
S9518
5
VDD VASTH AUTOSTORE CYCLE IN PROGRESS
VOLTS (V)
VASEND tASTO STORE TIME
TIME (ms)
2017 ILL5.0
FIGURE 3. AUTOSTORE CYCLE TIMING DIAGRAM
Notes: VASTH - AUTOSTORE threshold voltage VASEND - AUTOSTORE cycle end voltage tASTO - AUTOSTORE cycle time (6) Typical values are for TA = 25C and nominal supply voltage. (7) This parameter is periodically sampled and not 100% tested.
tDB UP
tGAP
1LSB Step VOUT
2017 ILL6.0
FIGURE 4. SLOW MODE TIMING
tDB UP
tS FAST
tS SLOW 1LSB Step VOUT 1 Second
2017 ILL7.0
FIGURE 5. FAST MODE TIMING
2017-04 4/24/99
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S9518
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP. .050 (1.270) TYP. 8 Places
.157 (4.00) .150 (3.80)
.275 (6.99) TYP.
1 .196 (5.00) .189 (4.80)
.030 (.762) TYP. 8 Places
FOOTPRINT
.061 (1.75) .053 (1.35) .020 (.50) x45 .010 (.25)
.0192 (.49) .0138 (.35)
.0098 (.25) .004 (.127) .05 (1.27) TYP.
.035 (.90) .016 (.40)
.244 (6.20) .228 (5.80)
8pn JEDEC SOIC ILL.2
ORDERING INFORMATION
S9518
S
Base Part Number
Package S = 8 Lead SOIC
2017 ILL8.0
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
(c) Copyright 1999 SUMMIT Microelectronics, Inc.
2017-04 4/24/99
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